1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit configured to generate a system clock for use in a microprocessor or the like.
2. Description of Related Art
In the prior art, in order to reduce electric power consumption, this type of semiconductor integrated circuit has been constructed to selectively use and control two oscillators of different oscillation frequencies so as to generate a necessary system clock to be supplied to a microprocessor, as shown in Japanese Patent Application laid-open Publication No. JP-A-61-109126.
Referring to FIG. 1A, there is shown a block diagram illustrating the system clock generating circuit (twin-clock control circuit) disclosed in Japanese Patent Application laid-open Publication No. JP-A-61-109126. The twin-clock control circuit, generally designated by Reference Numeral 3, includes a selector 5 coupled to two oscillators 1 and 2 of different oscillation frequencies and controlled by a microprocessor 4, and a system clock generation circuit 9 coupled to an output of the selector 5 so as to receive a clock generated by a selected oscillator and to generate a system clock to the microprocessor 4.
In the circuit shown in FIG. 1A, the oscillator 1 is configured to generate system clock of a sufficiently high frequency to meet with a high speed processing of the microprocessor 4. This system clock will be called a "main clock" hereinafter. The oscillator 2 is adapted to produce a clock corresponding to a low processing speed of the microprocessor 4. This clock will be called a "sub clock" hereinafter, and is used for a low power consumption operation of the microprocessor. The main and sub clocks are supplied from the oscillators 1 and 2 to the selector 5, in which either of the main and sub clocks is selected under control of the microprocessor 4, and then, supplied to the system clock generation circuit 9. In response to the clock selected by the selector 5, the system clock generation circuit 9 generates a high or low speed system clock, which is then supplied to the microprocessor 4.
Turning to FIG. 1B. there is shown another conventional twin-clock control circut. In FIG. 1B, elements similar or corresponding to those shown in FIG. 1A are given the same Reference Numerals, and explanation thereof will be omitted for simplification of description.
As seen from a comparison between FIGS. 1A and 1B, the second conventional twin-clock control circuit is featured in that the selector 5 receives the output of the oscillator 2 through a frequency multiplying circuit 10.
Accordingly, the main clock generated by the oscillator 1, and a clock obtained by frequency-multiplying the sub clock generated by the oscillator 2 by action of the frequency multiplying circuit 10, are supplied to the selector 5, so that either of the two clocks is selected under control of the microprocessor 4, as similarly to the first conventional twin-clock control circuit. Furthermore, similarly to the first conventional twin-clock control circuit, the system clock generation circuit 9 receives the clock selected by the selector 5, and generates a system clock, which is then supplied to the microprocessor 4.
In a semicondutor integrated circuit including the above-mentioned conventional twin-clock control circuit, when the main clock is stopped and the sub clock is selected so that the microprocessor operates on the basis of the system clock generated from the sub clock, the microprocessor is set in an operating mode for saving electric power (electric power saving mode). Namely, only the oscillator of a necessary minimum frequency is caused to operate. Accordingly, the processing speed of the microprocessor based on the sub clock may become too low, namely, greatly lower than a necessary or acceptable minimum processing speed.
In addition, in the case of using the frequency multiplying circuit, since the frequency multiplying circuit is required to have extremely high precision, circuit designing becomes very difficult. A reason for this is because the frequency multiplying circuit is inherently unstable against variations in temperature.